This invention relates to MOSgated devices and more specifically relates to a polysilicon MOSgated device build on a silicon carbide (SiC) diode substrate.
Silicon carbide has many properties which are very desirable in MOS gated devices, for example, power JEFTs, MOSFETs, IGBTs, MOScontrolled thyristors and the like. For example, the very high band gap of SiC permits very high blocking voltage and its ability to operate at very high temperature permits the use of high current density. It is well known that single diffusions can be formed in an SiC substrate, but the diffusion time required is very long as compared to the time required to diffuse junctions into a monocrystalline silicon substrate. The formation of sequential diffused junctions of different conductivity types, as necessary for the formation of channel regions of one conductivity type and source regions of another type, are very difficult to form in an SiC substrate.
It would be very desirable to employ the desired characteristics of SiC for a MOSgated device without the need for the sequential formation of different conductivity type regions in the SiC substrate.
In accordance with the present invention, a silicon FET (particularly polysilicon) is formed atop an SiC diode to define a MOSgated device with the desired thermal and voltage withstand characteristics of the SiC substrate, without requiring further diffusion into the SiC diode substrate. Thus, a lower polysilicon layer of the opposite conductivity type (which will contain the inversion region of the MOSgated device) to that of the substrate body is first deposited atop the surface of a SiC diode substrate having laterally spaced diode junctions diffused therein.
This layer is deposited undoped, and is implanted as with boron, to the desired resistivity. The top surface of this lower layer is then masked, and windows are formed to permit the implant of laterally spaced N+ source regions overlying the positions of the SiC diodes, and an N+ drain region located centrally between the SiC diode diffusions.
The top surface of the lower polysilicon layer is then oxidized to produce a silicon dioxide gate insulation layer having a thickness of, for example, 1000xc3x85. A conductive polysilicon gate layer (an upper poly layer) is then grown atop the gate oxide layer and is covered with an interlayer oxide.
The interlayer is photolithographically processed to open windows to enable contact to the N+ source regions in the lower polysilicon layer and thus to the diode diffusions in the SiC. An inversion layer is formed in the lower undoped polysilicon layer between the N+ source and N+ drain regions and the gate oxide interface.
The forward blocking voltage is then supported primarily by the depletion of the SiC drain between the spaced diode junctions, and only a small portion of the voltage is held off by the polysilicon FET. The device conducts in the usual manner of a MOSFET.